SoC Design / Integration Engineer
Integrate processors, memories, buses, interrupts and peripherals into complete memory-mapped systems, with emphasis on address maps, subsystem interfaces and IP integration.
Practice problems
Use these exercises to build the core implementation and verification skills for this path.
Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.Asynchronous-Assert Reset Synchronizer
Create a two-flop reset synchronizer with asynchronous assertion and synchronous deassertion.SoC Address Decoder
Decode the processor address into ROM, RAM, UART, GPIO and timer chip-selects.Memory-Mapped GPIO
Create a memory-mapped GPIO peripheral with an output register and sampled input register.Machine Timer Peripheral
Implement a free-running 32-bit timer and programmable compare register.Interrupt Controller
Combine UART, GPIO and timer interrupt requests into one CPU interrupt plus a cause code.
Implement a source register that obeys ready/valid protocol semantics.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.Asynchronous-Assert Reset Synchronizer
Create a two-flop reset synchronizer with asynchronous assertion and synchronous deassertion.SoC Address Decoder
Decode the processor address into ROM, RAM, UART, GPIO and timer chip-selects.Memory-Mapped GPIO
Create a memory-mapped GPIO peripheral with an output register and sampled input register.Machine Timer Peripheral
Implement a free-running 32-bit timer and programmable compare register.Interrupt Controller
Combine UART, GPIO and timer interrupt requests into one CPU interrupt plus a cause code.
Projects for this path
Use the projects to combine individual skills into larger portfolio-ready systems.
Small RISC-V SoC
Integrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.SoC Peripheral Subsystem
Build a reusable APB peripheral subsystem with reset control, decoding, response muxing, GPIO, timer, UART registers and interrupt aggregation.I²C Peripheral / Slave
Build the slave side of I²C from START/STOP detection and address matching through ACKs, byte RX/TX, register addressing and open-drain control.AXI4 Interconnect / Crossbar
Build a two-master, three-slave interconnect with address decoding, fair arbitration, ownership locking, response routing and DECERR handling.AXI4-Lite Slave Peripheral
Build a realistic memory-mapped RTL peripheral with independent AXI-Lite channels and correct response handling.AXI-Lite to APB Bridge
A realistic SoC integration block that exercises protocol and control-path reasoning.DMA Engine
Build the data-movement engine accelerators need: programmable registers, source/destination sequencing, backpressure, transfer counting and completion interrupts.UART Controller
Build a complete serial controller from timing generation through transmit, receive and loopback integration.
Open the interactive SoC Design / Integration Engineer roadmapIntegrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.SoC Peripheral Subsystem
Build a reusable APB peripheral subsystem with reset control, decoding, response muxing, GPIO, timer, UART registers and interrupt aggregation.I²C Peripheral / Slave
Build the slave side of I²C from START/STOP detection and address matching through ACKs, byte RX/TX, register addressing and open-drain control.AXI4 Interconnect / Crossbar
Build a two-master, three-slave interconnect with address decoding, fair arbitration, ownership locking, response routing and DECERR handling.AXI4-Lite Slave Peripheral
Build a realistic memory-mapped RTL peripheral with independent AXI-Lite channels and correct response handling.AXI-Lite to APB Bridge
A realistic SoC integration block that exercises protocol and control-path reasoning.DMA Engine
Build the data-movement engine accelerators need: programmable registers, source/destination sequencing, backpressure, transfer counting and completion interrupts.UART Controller
Build a complete serial controller from timing generation through transmit, receive and loopback integration.