Formal Verification Engineer
Prove RTL safety, ordering and progress properties using assertions, assumptions, bounded liveness, cover goals and protocol invariants.
Practice problems
Use these exercises to build the core implementation and verification skills for this path.
Valid Must Eventually Handshake
Write an assertion for a ready/valid interface.Reset Clears State
Verify that a synchronous reset clears a counter on the next clock edge.Formal Reset Assumptions
Constrain the formal environment so reset is asserted initially and then released.FIFO Safety Properties
Prove that FIFO occupancy never leaves its legal range.FIFO Ordering Property
Track one symbolic item and prove that the FIFO cannot reorder it.Arbiter Mutual Exclusion
Prove that an arbiter never grants more than one requester simultaneously.Bounded Arbiter Liveness
Prove a bounded progress guarantee for a requester that stays asserted.Ready/Valid Stability Proof
Prove that a source obeys ready/valid backpressure semantics.Formal Cover Goals
Use cover properties to prove interesting states are reachable, not merely safe.
Write an assertion for a ready/valid interface.Reset Clears State
Verify that a synchronous reset clears a counter on the next clock edge.Formal Reset Assumptions
Constrain the formal environment so reset is asserted initially and then released.FIFO Safety Properties
Prove that FIFO occupancy never leaves its legal range.FIFO Ordering Property
Track one symbolic item and prove that the FIFO cannot reorder it.Arbiter Mutual Exclusion
Prove that an arbiter never grants more than one requester simultaneously.Bounded Arbiter Liveness
Prove a bounded progress guarantee for a requester that stays asserted.Ready/Valid Stability Proof
Prove that a source obeys ready/valid backpressure semantics.Formal Cover Goals
Use cover properties to prove interesting states are reachable, not merely safe.
Projects for this path
Use the projects to combine individual skills into larger portfolio-ready systems.
Formal Verification of RTL Interfaces
Move beyond simulation by proving FIFO, arbiter and ready/valid properties with assumptions, assertions, bounded progress and reachability goals.Formal Verification of a Cache Controller
Prove cache invariants around hits, dirty eviction, refill ordering and bounded progress, then add reachability cover goals.Asynchronous FIFO / CDC
Build the Gray-pointer, synchronizer and full/empty logic behind a production-style dual-clock FIFO.UVM AXI4-Lite Verification Environment
Build a reusable verification environment with transaction-level stimulus, passive monitoring, scoreboarding, coverage and protocol assertions.RISC-V Core Verification
Verify architectural retirement with constrained-random instructions, a reference model, scoreboarding, assertions and functional coverage.
Open the interactive Formal Verification Engineer roadmapMove beyond simulation by proving FIFO, arbiter and ready/valid properties with assumptions, assertions, bounded progress and reachability goals.Formal Verification of a Cache Controller
Prove cache invariants around hits, dirty eviction, refill ordering and bounded progress, then add reachability cover goals.Asynchronous FIFO / CDC
Build the Gray-pointer, synchronizer and full/empty logic behind a production-style dual-clock FIFO.UVM AXI4-Lite Verification Environment
Build a reusable verification environment with transaction-level stimulus, passive monitoring, scoreboarding, coverage and protocol assertions.RISC-V Core Verification
Verify architectural retirement with constrained-random instructions, a reference model, scoreboarding, assertions and functional coverage.