Formal Reset Assumptions
Constrain the formal environment so reset is asserted initially and then released.
Task
Write one initial-state assumption requiring reset low at time zero and another property preventing reset from reasserting after it has been released.
Examples
- Implement the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this stage is verification-only.
Concepts to review
formal, assume property, reset
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Related problems
- Reset Clears State — Easy
- Asynchronous-Assert Reset Synchronizer — Medium
- Clock and Reset Generator — Easy
- Per-Domain Reset Synchronizer — Medium
- FIFO Safety Properties — Hard