Ready/Valid Stability Proof
Prove that a source obeys ready/valid backpressure semantics.
Task
When valid is high and ready is low, assert valid remains high and payload remains stable on the next cycle.
Examples
- Implement the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this stage is verification-only.
Concepts to review
formal, ready-valid, SVA
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Related problems
- Ready/Valid Skid Buffer — Hard
- Backpressure-Safe Ready/Valid Source — Medium
- Valid-Ready Streaming Accumulator — Hard
- Two-Entry Elastic Buffer — Hard
- Single-Entry Bypass Buffer — Hard