RTL Design Practice Problems
Use this path for digital-design and RTL interviews. Every problem asks you to turn a behavioral requirement into explicit synthesizable state, update rules and edge-case handling.
How to use this practice path
Stage 1
Define outputs and state before coding.
Define outputs and state before coding.
Stage 2
State reset semantics and cycle timing explicitly.
State reset semantics and cycle timing explicitly.
Stage 3
Handle simultaneous controls, boundaries and wraparound.
Handle simultaneous controls, boundaries and wraparound.
Stage 4
Explain how you would verify the block after writing RTL.
Explain how you would verify the block after writing RTL.
Problems to solve
2:1 Multiplexer
Design a synthesizable 2:1 multiplexer.
Parameterized Counter
Build a parameterized synchronous up-counter with reset.
Shift Register
Build a parameterized register that stores multiple bits and can shift its contents by one position on each clock edge.
Rising Edge Detector
Generate a one-cycle pulse whenever an input signal transitions from 0 to 1.
3-to-8 Decoder
Decode a 3-bit input into a one-hot 8-bit output.
16-bit Magnitude Comparator
Compare two unsigned 16-bit values.
Even-Parity Generator
Generate the parity bit required to make an 8-bit word have even parity.
Register with Clock Enable
Build an 8-bit register that updates only when enable is high.
Toggle Flip-Flop
Toggle an output bit whenever toggle_en is asserted.
Sticky Status Flag
Latch an event until software explicitly clears it.
Start/Busy/Done Controller
Implement a standard operation-control shell with start, busy and one-cycle done.
RISC-V Program Counter
Build the 32-bit program-counter register used by the guided RISC-V CPU project.
RISC-V Instruction Decoder
Slice the fixed RV32I instruction fields used by the rest of the CPU datapath.
UART Baud Tick Generator
Create the timing pulse that advances the UART transmitter and receiver.
UART TX Frame Shifter
Build the shift register that serializes a UART frame.
UART RX Start-Bit Detector
Detect the beginning of an incoming UART frame.
AXI-Lite Register Bank
Create the memory-mapped state that the AXI-Lite slave will expose.
Async FIFO Dual-Port Memory
Create storage that can be written and read from different clock domains.
Binary-to-Gray Pointer Conversion
Convert a binary pointer to Gray code so only one bit changes per increment.
Async FIFO Empty Detection
Determine when the read pointer has caught up with the synchronized write pointer.
Interview routine
For each problem, first restate the requirement and assumptions. Then write the RTL, assertion, verification component or architecture derivation without looking at a solution. Before running anything, list at least three edge cases. Finish by explaining how you would verify the result and what trade-offs you made.
Keep going
Use the interactive HDLForge problem workspace, browse company-style tracks, or choose a hardware project that uses the same skills.
Related implementation guides
- Verilog FIFO Design Guide — Learn synchronous FIFO RTL in Verilog: pointers, occupancy, full/empty logic, simultaneous read/write behavior and verification edge cases.
- Ready/Valid Handshake RTL Guide — Design ready/valid RTL correctly with backpressure, payload stability, skid buffers, elastic pipelines and executable HDLForge practice problems.