Design Verification Practice Problems
This path targets design-verification interviews. It combines SystemVerilog language semantics, temporal assertions and UVM transaction flow rather than treating them as isolated topics.
How to use this practice path
Stage 1
Start with SystemVerilog constructs and signal ownership.
Start with SystemVerilog constructs and signal ownership.
Stage 2
Add assertions for reset, handshakes and temporal requirements.
Add assertions for reset, handshakes and temporal requirements.
Stage 3
Trace transactions through driver, monitor and scoreboard paths.
Trace transactions through driver, monitor and scoreboard paths.
Stage 4
For each problem, identify stimulus, checking and coverage separately.
For each problem, identify stimulus, checking and coverage separately.
Problems to solve
always_comb vs always_ff
Identify the correct procedural blocks for combinational and sequential logic.
Reset Clears State
Verify that a synchronous reset clears a counter on the next clock edge.
Clock and Reset Generator
Create reusable testbench clock and reset stimulus.
Reusable Stimulus Task
Encapsulate repeated stimulus in a SystemVerilog task.
Self-Checking Adder Testbench
Make a simple combinational testbench report mismatches automatically.
Simulation Timeout Watchdog
Prevent a hung test from running forever.
Monitor-Only Interface Modport
Expose a read-only monitor view of an interface.
One-Hot Grant Assertion
Assert that an arbiter never grants more than one requester.
No FIFO Overflow Assertion
Assert that a write is never attempted while the FIFO is full.
No FIFO Underflow Assertion
Assert that a read is never attempted while the FIFO is empty.
Mutual Exclusion Assertion
Assert that read_active and write_active are never high together.
Constrain Address Range
Constrain a randomized address to a legal MMIO window.
Basic Coverpoint Bins
Measure whether low, mid and high values have been observed.
Ignore Uninteresting Coverage Range
Exclude irrelevant values from coverage closure.
UVM Test Objections
Control UVM test lifetime with phase objections.
SystemVerilog Interface
Create an interface for a simple ready/valid transaction channel.
Valid Must Eventually Handshake
Write an assertion for a ready/valid interface.
Build a UVM Driver
Implement the core run phase of a UVM driver for a simple transaction.
Queue-Based Expected-Value Checker
Use a queue to align expected outputs with a variable-latency DUT.
Randomized RTL Stimulus Loop
Generate repeatable pseudo-random input combinations.
Interview routine
For each problem, first restate the requirement and assumptions. Then write the RTL, assertion, verification component or architecture derivation without looking at a solution. Before running anything, list at least three edge cases. Finish by explaining how you would verify the result and what trade-offs you made.
Keep going
Use the interactive HDLForge problem workspace, browse company-style tracks, or choose a hardware project that uses the same skills.
Related implementation guides
- UVM Scoreboard Guide — Build a practical UVM scoreboard with monitor transactions, reference-model prediction, analysis connections, mismatch reporting and coverage-aware verification.
- SVA Handshake Assertions Guide — Write SystemVerilog Assertions for ready/valid and bus handshakes: VALID hold, payload stability, responses, reset disabling and backpressure.
- AXI-Lite Verification Guide — Learn how to verify AXI-Lite RTL with independent channel handshakes, assertions, scoreboards, backpressure tests and executable HDLForge practice.