Embedded Hardware / Firmware Engineer
Bridge RTL and software through memory-mapped peripherals, serial interfaces, interrupts, timers and small processor-based systems.
Practice problems
Use these exercises to build the core implementation and verification skills for this path.
UART Transmitter
Design an 8-N-1 UART transmitter.SPI Master
Implement a basic SPI mode-0 master for byte transfers.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.Programmable Clock Divider
Create a programmable divide-by-N toggle output.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.RISC-V Load/Store Control
Decode memory operations into read, write and register-writeback control signals.Memory-Mapped GPIO
Create a memory-mapped GPIO peripheral with an output register and sampled input register.Machine Timer Peripheral
Implement a free-running 32-bit timer and programmable compare register.Interrupt Controller
Combine UART, GPIO and timer interrupt requests into one CPU interrupt plus a cause code.
Design an 8-N-1 UART transmitter.SPI Master
Implement a basic SPI mode-0 master for byte transfers.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.Programmable Clock Divider
Create a programmable divide-by-N toggle output.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.RISC-V Load/Store Control
Decode memory operations into read, write and register-writeback control signals.Memory-Mapped GPIO
Create a memory-mapped GPIO peripheral with an output register and sampled input register.Machine Timer Peripheral
Implement a free-running 32-bit timer and programmable compare register.Interrupt Controller
Combine UART, GPIO and timer interrupt requests into one CPU interrupt plus a cause code.
Projects for this path
Use the projects to combine individual skills into larger portfolio-ready systems.
RISC-V Firmware + Hardware Bring-Up
Use C to bring up the memory-mapped hardware around a small RISC-V SoC: MMIO helpers, GPIO, UART, timer interrupts, command handling and a complete boot demo.SPI Controller
Build a configurable SPI master from clock generation and edge timing through MOSI/MISO shifting, chip-select control and complete multi-mode transfers.I²C Peripheral / Slave
Build the slave side of I²C from START/STOP detection and address matching through ACKs, byte RX/TX, register addressing and open-drain control.UART Controller
Build a complete serial controller from timing generation through transmit, receive and loopback integration.SoC Peripheral Subsystem
Build a reusable APB peripheral subsystem with reset control, decoding, response muxing, GPIO, timer, UART registers and interrupt aggregation.Small RISC-V SoC
Integrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.AXI4-Lite Slave Peripheral
Build a realistic memory-mapped RTL peripheral with independent AXI-Lite channels and correct response handling.DMA Engine
Build the data-movement engine accelerators need: programmable registers, source/destination sequencing, backpressure, transfer counting and completion interrupts.
Open the interactive Embedded Hardware / Firmware Engineer roadmapUse C to bring up the memory-mapped hardware around a small RISC-V SoC: MMIO helpers, GPIO, UART, timer interrupts, command handling and a complete boot demo.SPI Controller
Build a configurable SPI master from clock generation and edge timing through MOSI/MISO shifting, chip-select control and complete multi-mode transfers.I²C Peripheral / Slave
Build the slave side of I²C from START/STOP detection and address matching through ACKs, byte RX/TX, register addressing and open-drain control.UART Controller
Build a complete serial controller from timing generation through transmit, receive and loopback integration.SoC Peripheral Subsystem
Build a reusable APB peripheral subsystem with reset control, decoding, response muxing, GPIO, timer, UART registers and interrupt aggregation.Small RISC-V SoC
Integrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.AXI4-Lite Slave Peripheral
Build a realistic memory-mapped RTL peripheral with independent AXI-Lite channels and correct response handling.DMA Engine
Build the data-movement engine accelerators need: programmable registers, source/destination sequencing, backpressure, transfer counting and completion interrupts.