RV32I Reference Model
Maintain a simple architectural register model for ADD, SUB and ADDI instructions.
Task
Implement a model class with 32 registers, x0 forced to zero, and an `execute()` method that updates the expected destination register.
Examples
- Complete the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this is a verification-only stage.
Concepts to review
RISC-V, reference model, ISA
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Related problems
- RISC-V Program Counter — Easy
- RISC-V Instruction Decoder — Easy
- RISC-V Register File — Medium
- RISC-V Immediate Generator — Medium
- RISC-V ALU — Medium